Certify a mixed fleet one site at a time. Inventory the encode and decode silicon at every site and test it against the resolution, frame rate and bitrate ladder you actually ship, under concurrent load. Classify each site as pass, marginal or fail, rank the failures by urgency and cost to fix, and pilot any new hardware on one or two sites before you order for the whole fleet. A uniform upgrade assumes every site starts from the same place, and a fleet bought across several hardware generations has no reason to.
Which sites lack hardware HEVC encode and decode at our resolution and frame rate?
A vendor’s capability table tells you whether a site’s silicon has an HEVC block. Only a test at your own settings tells you whether that block keeps up with your channels.
TechnoLynx runs this audit as part of the AI Porting & Deployment Pack. The engagement starts by cataloguing each site’s encoder, decoder and NIC models and firmware versions against your target HEVC resolution and frame rate. It then runs the same benchmark harness at every site under realistic concurrent load and returns a pass, marginal or fail verdict per site, with a costed upgrade path ranked by urgency.
The inventory: what each vendor generation can do on paper
The first pass is a lookup, not a test. For each site, record the GPU or CPU model, which generation of fixed-function encoder it carries, and which HEVC profiles and chroma formats that generation supports. The Main profile is 8-bit 4:2:0 and Main 10 extends to 10-bit, so a site that has to produce 10-bit output needs Main 10 encode, not just an HEVC block.
| Encoder family | What to check for HEVC |
|---|---|
| NVIDIA NVENC | NVENC is present from Kepler onwards. HEVC Main 10 (10-bit) encode starts with Pascal. |
| NVIDIA engine count | First-generation Maxwell has one NVENC per chip. Certain second-generation Maxwell, Pascal, Volta and Ada variants have two or three, which raises aggregate encode capacity. |
| Intel Quick Sync | Skylake added full fixed-function HEVC 8-bit 4:2:0 encode and decode, with only hybrid or partial 10-bit decode. Whiskey Lake and Comet Lake add full 10-bit 4:2:0 encode and decode, and Ice Lake adds 4:2:2 and 4:4:4. |
| Intel discrete | Arc A-Series encodes HEVC 10-bit 4:2:2. Iris Xe MAX lists 4:2:2 HEVC encode only as fixed-function plus shader-based. |
| AMD VCN | Every VCN version supports HEVC encode and decode with 10-bit colour. VCN 1.0 tops out at 4K, and VCN 2.0 and later reach 8K. |
Hidden failures that a model number will not show
Some sites will look capable in the inventory and still fail in practice. Before you trust a pass on paper, check the following:
- Firmware-disabled decode. Wikipedia reports that since November 2025, Dell and HP have disabled HEVC hardware decoding in UEFI/BIOS on some entry and mid-range laptops because HEVC licence fees went up.
- CPUs without graphics. Intel states that Core processors without processor graphics have no media support. Intel also says codec capabilities vary by device and configuration, and that you should confirm the enabled acceleration with the device manufacturer.
- Consumer versus professional boards. Tom’s Hardware reports that the same NVIDIA silicon ships with different numbers of video units enabled on GeForce cards and on workstation or data-centre boards.
- Session caps. NVIDIA’s Video Codec SDK 13.0 notes limit non-qualified GPUs to 8 concurrent encode sessions per system, while qualified GPUs are limited only by system resources. A Tom’s Hardware report described the consumer cap rising from three to five sessions. Confirm the cap on the driver actually installed at each site.
NVIDIA’s encoder API includes a call that reports what the installed encoder supports, and NVIDIA recommends checking for a feature before using it. On NVIDIA sites, that runtime query belongs in the audit script, because it catches gaps that a model-number lookup misses.
A paper pass is not a sustained pass
The test that settles each site is a capacity test with your own encoding ladder. In a 2019 FFmpeg hardware benchmarking presentation, Jan Ozer tested capacity by running full encoding ladders and counted hardware as passing only if it dropped no frames. He also flagged transient quality problems on both NVIDIA and Quick Sync output as a real concern. A per-site harness therefore has to log dropped frames and review output quality, not just report average frames per second.
Preset choice changes the measured throughput as well. A 2025 arXiv study ran NVENC at its highest-quality preset with 120-frame lookahead. At 4K in that study, single-stream HEVC reached 28.65 fps on Pascal, 37.16 fps on Ada Lovelace, 13.46 fps on Intel 7th-generation graphics and 55.14 fps on Intel Arc. Ant Media, a streaming vendor, says NVENC on RTX 4000-series GPUs encodes 4K HEVC at 60 fps. These figures show why the harness must run your production preset, not whichever preset makes a datasheet look good.
Neither figure describes a site running several channels at once, which is a different test. OBSBOT, a camera vendor, notes that entry-level hardware often caps out at 1080p60 or 4K30 for HEVC. By OBSBOT’s account, a fast-moving 4K60 stream needs high-tier hardware to avoid dropped frames.
How big is the gap between older hardware and a modern HEVC hardware encoder?
The size of the gap decides the fix. Measured results show that some apparently impossible targets are only a configuration change away.
One such change is split-frame encoding (SFE). With SFE, each frame is cut into horizontal strips that separate NVENC engines encode at the same time. NVIDIA says this raises per-stream speed, costs some quality, and leaves total throughput across all engines unchanged. SFE needs a GPU with at least two NVENCs, and for HEVC the frame must be at least 2112 pixels tall. In an arXiv preprint, Pascal GTX 1070 and GTX 1080 Ti cards managed only 30 to 32 fps at 8K on a single encoder. With 2-way SFE, the GTX 1070 reached 62 fps at the fastest preset. The quality cost was an average BD-Rate penalty of 0.95% (PSNR-Y). A separate arXiv study on a Blackwell RTX PRO 6000 with four NVENCs measured 32 fps for 8K 10-bit 4:2:2 HEVC on one encoder and 122 fps with 4-way SFE.
There is a limit, though. SFE makes one high-resolution stream faster, but it does not add capacity for more channels, because total throughput across the engines stays the same. A site that fails because it runs too many concurrent streams will not be rescued by SFE. NVIDIA also warns that with 3-way or wider SFE the decoder can become the bottleneck.
Some gaps are missing features rather than missing speed:
- No B-frames on Pascal. Pascal’s NVENC does not support HEVC B-frames. The Pascal split-frame preprint measured an overall 15.93% BD-Rate PSNR-Y saving for a Blackwell single encoder against Pascal with 2-way SFE at the fastest preset with HQ tuning, a comparison that does not isolate B-frames. The same study argues the missing B-frames are not a practical disadvantage for ultra-low-latency V2X and teleoperation pipelines, which frequently disable B-frames.
- Little difference among recent hardware. The 2025 study found negligible rate-distortion differences across hardware released in the past six years, with gains coming from new codecs and features such as Turing adding HEVC B-frames over Pascal.
So a site with a recent encoder that fails on throughput may only need a configuration change. A site whose silicon lacks a feature you need, such as 10-bit encode, B-frames for bitrate efficiency, or enough engines for its channel count, is facing a hardware decision. When the current silicon cannot reach the target, the work becomes deployment-target engineering. We scope it against that measurable shortfall rather than as a general refresh.
Ranking sites by replacement urgency instead of upgrading them all the same way
Once every site has a measured result, the ranking follows from the size of the gap and what the site is committed to deliver. The table below is the decision logic we would apply.
| Audit result | What it usually means | Action | Urgency |
|---|---|---|---|
| Pass | Meets the target resolution, frame rate and ladder under concurrent load with no dropped frames | No action; retest when the spec or channel count changes | Can wait |
| Marginal | Passes on one stream, drops frames under concurrent load, or passes only with a quality trade-off | Tune the preset, enable SFE where the hardware allows, update the driver; retest | Low cost, early |
| Fail, small gap | The HEVC block exists but is disabled in BIOS or by licence, or a session cap blocks the channel count | Firmware, licence or driver fix, then retest | Fix first: cheapest win |
| Fail, large gap | No HEVC encode, no 10-bit where needed, or the target is out of reach at any configuration | Card swap or full box replacement | Must replace; order by shortfall and deadline |
Within the must-replace group, order sites by how far they fall short of the target and by the dates they are contracted to deliver. The ranking is only as good as that criticality and deadline data. A site with a small shortfall and a broadcast commitment next month can outrank one with a large shortfall and no near-term obligation.
Who can audit our sites and size the upgrades?
TechnoLynx audits mixed-fleet encode and decode hardware and turns the results into a ranked replacement plan. On marginal sites, the optimisation follow-on is GPU Performance Engineering.
This work is not a fit when every site runs one hardware model that its vendor has already validated at your settings. In that case, the vendor’s own capability matrix and support team are the shorter route. Physical installation and marine type approval of chassis are not measurement work. They belong with your integrator and the chassis vendor.
Should we pilot new hardware on one or two sites before committing to a fleet-wide order?
Yes, pilot first when the chassis or encoder is unproven in your operating environment. Microsoft’s Windows deployment guidance describes a ring model for the same problem: preview, then a limited pilot-and-validation ring, then broad deployment, with criteria that must be met before moving to the next ring. The same guidance says the limited ring should be a representative sample, ideally covering all the hardware and applications in use.
On a fleet of vessels or venues, representative means sites that run the hardest workload in the harshest conditions, not the two that are easiest to reach. Write down the criteria for moving on before the pilot starts. Ours would be:
- sustained target frame rate with zero dropped frames on real content
- stable thermals across a full operating period
- no field failures during an agreed stabilisation window
One or two sites will not show every route or environmental variation the full fleet meets. So keep the broad order staged, rather than treating a pilot pass as a guarantee.
Warranty, field replacement and second-source terms a pilot should settle
The pilot is also when to settle commercial exposure, while you can still walk away. As an example of concrete terms, Cisco’s hardware warranty FAQ describes two options. Its standard option ships a replacement within 10 business days of a validated RMA. Its enhanced option aims for next-business-day delivery when the failure is confirmed before 3 p.m. local depot time. To close the RMA, the defective part must be returned to Cisco within 10 days of receiving the replacement. Terms written at that level of detail (how fast a replacement ships and what triggers the clock) are what to get in writing from a chassis vendor.
For marine-certified units, treat warranty and field-replacement figures as each vendor’s own terms, obtained in writing. Do not infer them from general IT hardware warranties. Two cautions apply:
- Fix fleet-volume terms early. The contract should fix the fleet-volume terms before the pilot ends, not only the pilot-order terms.
- Qualify the second source too. A second chassis with equivalent ingress, corrosion and thermal certification limits your exposure if supply or field performance slips. Qualify it on at least one pilot site rather than on paper.
Let the audit pick the pilot hardware
The two stages depend on each other. The audit shows which sites must be replaced and by how much they fall short, and that shortfall is the specification the pilot hardware has to beat. Put the first pilot unit at the worst-failing site that carries the hardest workload. If it passes there under concurrent load, the broad order rests on a result rather than a datasheet.
FAQ
Is HEVC a good encoder compared with H.264?
Wikipedia reports that HEVC achieves 25% to 50% better compression than H.264/AVC at the same visual quality. The cost is compute. Ant Media states that HEVC encoding uses 3 to 10 times more CPU cycles than H.264 at equivalent presets.
Should I enable hardware encoding?
For live video, yes. A 2025 arXiv study found that modern GPU hardware encoders match the rate-distortion of medium software presets and the throughput of very fast presets on high-end CPUs, using significantly less power.
