Qualifying a second-source component takes months, not weeks. In our judgement, a supplier qualification process the capital-equipment committee can approve has four parts. It documents in advance the qualification requirements the alternate part must meet. It runs the independent workstreams in parallel. It checks the new vendor’s lead-time claims instead of accepting the quote at face value. And it covers the supply gap with contractual buffer stock or scheduled NCNR orders until production approval comes through.
TechnoLynx handles the software part of that plan for a vision SoC. Through the AI Porting & Deployment Pack, its engineers set the workloads and accuracy criteria the alternate must match, audit the porting risk in its compute stack, and produce the evidence package for sign-off. The first step is agreeing those acceptance criteria with your team.
How long second-source qualification takes for a part like a vision SoC
SupplyICs sorts second sources into three tiers. A true drop-in has the same package, pinout and electrical specifications, and takes 8-16 weeks for commercial or industrial use and 16-26 weeks for automotive. A part that does the same job on the same footprint but has different register maps or peripherals needs firmware work, and takes 16-32 weeks for commercial or industrial and 26-52 weeks for automotive. A part that needs a new PCB layout takes at least 26-52 weeks, plus the time and cost of a board respin.
The measured medians are longer than those effort estimates. SupplyICs cites a 2025 Semiconductor Industry Association benchmarking study that put the median time from identifying a second source to production approval at 14 months for automotive, 10 months for industrial and 7 months for commercial or consumer applications. The same study found that companies that started qualifying before a shortage were 4.7 times more likely to avoid production disruption than companies that started during one. SupplyICs puts production readiness 12-18 months away for a programme starting now.
We would not treat an alternate vision SoC as a Tier 1 drop-in. Plan for Tier 2 at best, and Tier 3 if the package changes.
Shorter figures do get quoted. AESTECHNO gives 8-12 weeks to qualify a second source for strained parts such as PMICs, DDR memory and MEMS sensors, where two suppliers are already available. That figure is AESTECHNO’s tier rule for parts with two suppliers already available. For a committee timeline we would rely on the SIA medians instead.
Some steps have a minimum duration that urgency cannot shorten. HAST still needs at least 96 hours and HTOL at least 1,000 hours for AEC-Q100 Grade 1, and software integration effort grows with firmware complexity, not with procurement urgency. There is one useful nuance. Component-level reliability data normally comes from the semiconductor manufacturer’s own qualification package. If the alternate already has that data, the buyer’s own testing is bench characterisation and an SMT pilot batch.
Which qualification steps run in parallel, and which have to wait
AESTECHNO’s practice is to start qualifying an alternative and evaluating a partial redesign at the same time, and to keep both options open until the following quarter. In a SupplyICs case, a pre-identified Tier 1 drop-in with parallel workstreams reached production approval in 14 weeks.
The validation sequence is a chain. Kynix describes a five-stage gate: desktop gap audit, dynamic bench stress, thermal and reliability screening, SMT pilot batch, then a scoped ECO release. The SMT pilot cannot be skipped just because the part passed on the bench, because hand soldering with a bench iron hides solder voiding under thermal pads and package warping.
| Workstream | When it can start | What it waits for |
|---|---|---|
| Supplier capability assessment and documentation review | Day one | Nothing |
| Lead-time and capacity verification | Day one | Nothing |
| Porting-risk audit of the compute stack | After framing the workloads | Agreed workload and accuracy criteria |
| Partial-redesign evaluation | Alongside alternate qualification | Nothing; kept open as a fallback |
| Bench stress and characterisation | After the desktop gap audit | Samples and gap-audit findings |
| Thermal and reliability screening | After bench stress | Bench results |
| SMT pilot batch | After reliability screening | Production-intent boards |
| Scoped release | Last | Pilot results, tied to named assemblies |
If the porting audit is still running when the pilot boards are built, a kernel problem found late can force another pilot.
The porting-risk audit for a second-source vision SoC
The audit starts below the brand name. Two parts can carry different brands and still come from the same foundry or the same OSAT assembly site, which makes that site a single point of failure. True independence means knowing the wafer fab, assembly site and test facility behind each part.
Next comes behaviour that a datasheet comparison misses. Kynix names silicon process node variation as the primary driver of second-source failure. The same logic built on a smaller node switches much faster and behaves differently in dynamic conditions.
On a vision SoC, we would expect most of the risk to sit in the software stack. A published case study ported numerical integration codes from CUDA to oneAPI. The authors had to map library calls to oneAPI equivalents, deal with optimisation differences between the NVCC and Clang compilers, and rework the build and test tooling. After those fixes, the oneAPI versions were at most 10% slower than optimised CUDA on the same NVIDIA V100. The slowest cases used far more registers than the CUDA originals, which reduced occupancy. Where register counts were similar, the penalty was below 5%. That study covers numerical integration codes on a data-centre V100 GPU, not vision pipelines on embedded silicon. The lesson that carries over is that the penalty was only known after the port was done, so the audit has to port and measure rather than estimate.
For an early read on candidate devices, LynxBenchAI’s published results show how each device runs the public PyTorch stack. They are broadly indicative for custom PyTorch models, but they do not run or measure your own vision pipeline. The wider manufacturing side of this work is covered under AI engineering for manufacturing and automotive.
Release the alternate only for the products it was tested for. An alternate approved for one product must not be released automatically for a more demanding product that shares the base part number. It should be released against named top-level assembly numbers in the PLM system.
Supplier qualification checklist: the minimum evidence for committee sign-off
USP General Chapter <1083> defines supplier qualification as a systematic evaluation of three things: the risk to product quality, the compliance of the supplier’s quality system, and the supplier’s reliability in avoiding quality deviations and shortages. It asks that each step be documented and justified, with effort proportional to the risk. It also calls for a cross-functional team with a named process owner. It is a pharmaceutical chapter, but that structure works just as well for a semiconductor buy.
| Evidence | What it should show |
|---|---|
| Component reliability data | JESD47 HTOL on 3 lots of 77 units, 1,000 hours, zero failures |
| Automotive qualification | AEC-Q100 stress-test data, or generic family data the supplier justifies and the user approves |
| Lifetime margin | 1,000 hours of HTOL at 125 °C equals about 9 years at 55 °C use (0.7 eV, per JESD47I), which may be shorter than the application needs |
| Bench characterisation | 5-10 serialised samples across voltage and temperature extremes |
| Assembly validation | An SMT pilot batch of 20-50 boards |
| Software parity | Correctness and performance on representative workloads, matched against the primary SoC |
| Supply independence | Wafer fab, assembly and test sites identified for both sources |
| PPAP availability (automotive) | Confirmed per orderable part, because an AEC-Q100 label does not guarantee PPAP |
| Requalification triggers | Agreed list, for example a minimum feature size reduction of more than 20% counts as a new process |
| Supply evidence | Verified lead time and capacity written into the order documents (covered below) |
AEC-Q100 requires requalification whenever a supplier change affects, or could affect, form, fit, function, quality or reliability.
Our decision rule for the committee is simple. Approve the plan if it covers supplier capability, steps clearly marked as parallel or sequential, a porting-risk audit and a timeline that fits the decision window. Escalate or delay if the porting-risk or lead-time findings are still open. Be careful when the date is set by business pressure rather than by readiness. In that case the honest thing to bring is the plan and the bridge, not a qualified part. We would build the fastest responsible route from four things: pick the lowest-tier candidate, rely on the manufacturer’s existing qualification data, start every independent workstream in the first week, and present the bridge alongside the plan.
Who can audit the porting risk on our second-source vision SoC?
TechnoLynx handles the software side of second-source qualification for an embedded vision SoC: proving your vision workloads run correctly and fast enough on the alternate silicon before the committee commits. The work starts by framing the problem, setting the workloads and the accuracy and performance criteria the second-source part must match. TechnoLynx then assesses the alternate’s compute stack (CUDA, ROCm or oneAPI), audits the hidden porting risk, and ports and optimises kernels and pipelines where that risk is real. TechnoLynx checks that correctness and performance match the primary SoC on representative workloads. The output is an evidence package and timeline for sign-off that records which steps ran in parallel and which had to wait. This engagement is the AI Porting & Deployment Pack.
The pack covers porting, not the hardware and commercial side. Reliability stress data, supplier quality audits, PPAP, counterfeit screening and contract negotiation belong with the manufacturer’s qualification package, accredited test labs, your supplier quality engineers and legal counsel. If your team already ships on both vendors’ SDKs and has ported this pipeline before, it may not need outside help for the port. The case for a specialist is strongest when the alternate’s toolchain is new to the team and the committee date is fixed.
How do we check a second-source vendor’s quoted lead time against its real backlog?
Ask for evidence of real capacity, not a better quote. That means historical output, current line loading, material readiness, and the rules the factory uses to reserve production slots. Quoted figures diverge from real supply performance. They often ignore lead times on the vendor’s own materials, lines shared with other programmes, and seasonal load, and a factory that looks open on the calendar may already have committed the relevant line elsewhere.
Verification guidance lists the concrete requests. Ask for anonymised recent orders with similar process steps and their actual dates from confirmation to shipment. Ask how long-lead materials are planned. Review the production calendar for the relevant lines, confirm which document or payment locks a production week, and ask how the factory handles rush orders that jump the queue. A factory that often breaks its own schedule for rush orders will break yours when someone else pays for priority.
Plan against the longest lead time, not the average. Kynix gives the example of one distributor showing a 4-week shortest, 12-week average and 26-week longest factory lead time, and another showing 6, 14 and 52 weeks. Recording only the average hides the 26-52 week tail. Gate decisions should test the longest factory lead time against the build dates.
Treat the vendor’s track record as data. AS9100 explicitly mentions on-time delivery in supplier monitoring, and you should be able to show the data. A simple scorecard after each shipment, comparing promised and actual lead time, quantity accuracy and communication, gives you that data for future allocation decisions. USP <1083> lists the ability to meet regular lead times and future manufacturing capacity among the requirements for a supplier, and allows remote audits or third-party certification where an on-site audit is not possible.
Patterns across recent orders matter more than a single best case. Look for consistency across sources rather than relying on any one of them. Our decision logic is to require a capacity review and references before signature. If neither is available, or the history is poor, add penalty terms or start looking for a third source. If line loading is tight, negotiate reserved capacity. Whatever you confirm should be written into the purchase agreement or a schedule appendix.
What contractual penalties can we put in place if lead times slip?
One remedy is a liquidated damages clause. It fixes a sum for a defined breach such as late delivery, so the buyer does not have to prove its loss or argue around liability caps. Published sample clauses show the structure. One charges 0.5% of the delayed equipment’s value per week, capped at 5%, and allows termination after 12 weeks. Another charges 0.1% per day, capped at 10%, with cancellation after 10 weeks. A third gives a 2-week grace period, then 0.5% per week, and allows termination after 4 weeks. Each of these excludes force majeure.
At 0.5% a week with a 5% cap, the penalty stops growing after 10 weeks (5 ÷ 0.5). Penalties work as an incentive for timely delivery. They do not compensate for a stopped line.
Fladgate points to three other terms. Termination for delay generally needs time of delivery to be stated expressly as “of the essence”, because otherwise only material or persistent breaches allow termination. A cover-cost clause lets the buyer recover the extra cost of buying from third parties, and counts those quantities against its purchase obligations. An express indemnity covers claims from the buyer’s own customers, which standard terms of sale usually exclude.
Under US law there are two limits. UCC § 2-718 allows liquidated damages only at an amount that is reasonable given the anticipated or actual harm, and treats an unreasonably large sum as a void penalty. UCC § 2-615 excuses delay when performance becomes impracticable, provided the seller allocates its remaining capacity fairly among customers and notifies the buyer in time of its estimated quota. So in a real shortage, a penalty clause guarantees allocation and notice, not supply.
Covering a 52-week lead time while the second source is qualified
Use several measures at once. Pull authenticated distributor or broker stock as an immediate stop-gap. Negotiate a contracted bridging buy from the primary vendor. Check the existing contract for remedies. And size a buffer to cover the qualification window, because that buffer is the structural fix whatever the other three produce.
A contracted buffer stock from the current vendor
A buffer stock agreement between Wisekey Semiconductors and Key Tronic shows how the mechanics work. Its stated purpose is to reduce the buyer’s supply lead time. The buyer provides a 12-month rolling forecast every month. The buffer is set at the average monthly quantity for the coming twelve months, adjusted for minimum order quantities, and is reviewed at the monthly forecast meeting. The vendor must replenish the buffer once it is drawn down, even partially. The vendor reports buffer levels in writing every month. It also refreshes stock to avoid date-code ageing.
That sizing matches average monthly demand. Roughly one month of demand cannot bridge a qualification that, at the SIA industrial median, runs for ten. For a bridge, size the stock to the realistic qualification window plus the ramp-up on the new source. You can use scheduled non-cancellable, non-returnable (NCNR) backlog orders or a last-time buy where the part is effectively sole-source. Before placing NCNR orders, confirm the defect and traceability warranties, require parts from recent factory lots rather than aged stock, and negotiate staggered deliveries. Staggered deliveries help cash flow but do nothing about long-term forecast error.
If the primary part is heading for end of life, industry standards set the window. Under JEDEC JESD48C and J-STD-048, manufacturers typically allow at least 6 months from the discontinuance notice for last orders, and 12 months in total for final shipments. After that, replenishment lead time becomes infinite.
Broker and distributor stock as a stop-gap
One white paper notes that modern counterfeits increasingly optimise for passing basic inspection and parts of SAE AS6171 testing, then fail under long-term stress such as thermal cycling and parametric drift. Scarcity also widens the price gap between authorised and unauthorised channels. Its recommendations are to use authorised channels and demand chain-of-custody evidence first, to buy from SAE AS6081-accredited independent distributors where brokers are needed, and to put urgent buys through a risk-based gate.
Screening can be matched to risk. For commercial parts, baseline optical inspection, solvent rub and solderability checks may be enough. Full destructive AS6171 analysis is kept for safety-critical or high-value parts. In aerospace, AS9100 and AS9120 auditors expect an unbroken documentation chain back to the original manufacturer, or else accredited testing. Before relying on broker parts in a shipped product, check whether they carry any manufacturer warranty.
Remedies against the primary vendor for the lead-time blowout
Whether you can claim anything depends on the clauses you signed. Vendor paper often closes the door: the same Wisekey agreement says delivery times are “only indicated approximately” and can never justify penalties, withholding of payment or cancellation. Where US sales law applies and the vendor claims impracticability, it still has to allocate fairly and tell you your estimated quota. We would ask for that quota in writing and plan the bridge around it. Contracts that require regular forecasts, even non-binding ones, give early warning of supply problems and a reason to talk before they become a stoppage.
| Bridge option | How fast | Main risk | What it covers |
|---|---|---|---|
| Broker stock | Immediate | Counterfeits that pass basic tests | A stop-gap only |
| Contracted buffer stock | Next order cycle | Sized to steady-state demand | Months, if sized to the qualification window |
| NCNR backlog or last-time buy | Next order cycle | Capital tied up, and stock you cannot return | Qualification window plus ramp-up |
| Contract remedies | Slow | Excluded or capped by the clauses | Cost, not supply |
Related contract and provisioning risks to check before switching silicon
AS9100 purchase-order terms commonly require suppliers to notify, and get approval for, changes to processes, products, providers or manufacturing location. If your customers’ contracts impose the same duty on you, adding an alternate SoC may require formal notice to them before release.
HSM provisioning architecture is one of the related risks to assess alongside qualification.
There is a pattern across all of this. The bridge, the penalty terms and the qualification plan rest on the same assumption about how long qualification will take, and the porting audit is the step most likely to change that assumption. If the audit finds a real kernel or toolchain gap, the buffer size and the committee date have to be revisited together.
FAQ
What are the criteria for supplier qualification?
USP <1083> evaluates suppliers on three things: the risk to the quality of what they supply, how well their quality systems comply with regulations and the contract, and how reliably they avoid quality deviations and shortages. Its list of appropriate requirements includes meeting regular lead times, future manufacturing capacity, material traceability and controls against counterfeit products.
What does “approved suppliers” mean?
An approved supplier is one listed on the Approved Vendor List (AVL) for a part. A part becomes a single-source risk when only one qualified manufacturer or sourcing option is on that list. A sole source (a market monopoly) is different from a part that is single-qualified only because no one has qualified an alternate yet, and the two need different fixes.
What does “qualification plan” mean?
A qualification plan is the documented set of steps, evidence and acceptance criteria a candidate supplier or part must meet, with the effort proportional to the risk. For a semiconductor second source, it sets out the electrical, software, reliability and regulatory requirements for each candidate.
