Take one printed-electronics line — solder paste, fine traces on a reflective substrate, a conveyor that will not slow down — and run the feasibility audit on it class by class. The verdict is never one number. On the workload described below, three defect classes come out feasible at line speed, two come out conditional on a lighting or fixturing change, and one comes out no-go with the imaging chain the line can currently support. That split is the deliverable. An off-the-shelf accuracy figure quoted on a public PCB dataset cannot produce it, because the figure is blended across classes and measured under conditions the line does not have.
This is a worked instance rather than a method write-up. The general shape of the audit — what it profiles, what it delivers, how it is scoped — is covered in our feasibility-audit approach to CV inspection in manufacturing. Here we walk one workload.
The line
A mid-volume printed-electronics assembly line: paste print, place, reflow, with an existing AOI station after reflow and a manual inspection bench handling escapes and adjudication. Board population is dense, substrate finish is reflective, and the QA records name six recurring defect families — solder-paste voids, trace opens, trace shorts and bridging, print registration drift, paste smearing, and substrate contamination. Warp appears occasionally and is logged separately.
The first move in the audit is not imaging. It is taking the defect catalogue from the line’s own QA records rather than from a vendor taxonomy, because the two rarely agree on granularity. In this case “solder-paste void” in the plant’s records covered both a shallow surface depression and a deep sub-pad void, which are different detection problems by an order of magnitude. Splitting that one label into two was the single highest-leverage decision in the audit, and it is a decision no benchmark number can make for you.
Why does defect-class granularity decide the whole verdict?
Because detectability is a physical property of the individual defect, not of the part or the model. A defect is detectable when it produces enough contrast, at enough pixels, at the exposure the line’s throughput allows. Bridging between two adjacent pads is a high-contrast, multi-pixel geometric change; a shallow paste void on a reflective pad is a low-contrast intensity gradient that specular highlight can erase entirely. Both are “paste inspection”. Their achievable accuracy bands are not close.
Once the catalogue is split honestly, the blended accuracy figure stops being usable — and that is the point. We see the same pattern across industrial CV scoping: the classes that decide whether the pilot is worth firing are exactly the low-contrast classes an aggregate figure hides. The general treatment of which defect physics survive imaging lives in our note on which defect classes are feasible for CV inspection today; this article applies it to one board.
The per-defect-class feasibility map
This is the core output of the audit for this workload. Detection and false-positive figures below are the measured result on this line’s own labelled samples at its target throughput — an operational measurement on one named workload, not a portable benchmark, and not a figure that transfers to another line with different optics.
| Defect class | Imaging condition it needs | Verdict | Constraint that decides it |
|---|---|---|---|
| Trace shorts / bridging | Diffuse dome light, current camera resolution | Feasible | High geometric contrast; resolvable at existing pixels-per-mm |
| Print registration drift | Fiducial-referenced capture, stable fixture | Feasible | Measurement problem, not a classification problem |
| Paste smearing | Diffuse light, existing exposure | Feasible | Large-area intensity change; tolerant of substrate variance |
| Trace opens (hairline thinning) | Higher pixels-per-mm; low-angle directional light | Conditional go | Needs an optics change; defect width sits near the current resolution floor |
| Shallow paste void (surface) | Multi-angle or structured illumination to suppress specularity | Conditional go | Reflective pad finish; specular highlight swamps the gradient |
| Deep sub-pad void | Not surface-visible | No-go | Imaging physics — requires X-ray, outside CV scope |
| Substrate contamination | Diffuse light; depends on contaminant type | Split verdict | Particulate feasible; transparent residue borderline |
| Substrate warp | Height measurement, not 2D intensity | No-go for 2D | Needs profilometry or structured-light 3D |
The two no-go rows are worth more to the buyer than the three feasible rows. A pilot sized to include sub-pad voids fails on physics no matter which model is selected, and it fails after the capex is spent.
Where the reflective substrate sets the ceiling
Solder paste on a reflective pad is specular. Under a single ring light at the geometry the line’s existing mounting allows, the highlight lands where the void is, and the intensity difference the model would key on disappears into saturation. That is not a labelling problem or a model-capacity problem; the information is not in the image.
Two remedies are available on this line, and both cost money before any model exists. Multi-angle illumination — capturing the same board under two or three sequential light directions and fusing the frames — recovers the gradient but multiplies capture time, which collides directly with the conveyor budget. Structured illumination gives a cleaner surface reconstruction but requires the board to be momentarily stationary, which this line’s indexing does not currently provide. So the shallow-void verdict is honest only when written as a conditional: feasible at a stated accuracy band if the line accepts either a lighting retrofit or an indexed stop, and no-go otherwise.
The imaging-condition side of this reasoning — illumination geometry, specularity, fixture repeatability, vibration — is developed as a general survey method in our CV inspection site survey for lighting, fixturing and conveyor conditions. What the printed-electronics case adds is how tightly the paste-specularity problem couples to throughput: on this workload you cannot fix the lighting without spending conveyor time, and you cannot spend conveyor time without renegotiating the line’s cycle.
Holding accuracy at production throughput
Measured accuracy on a bench survives to production only if the line holds the conditions the measurement was taken under. For this workload the audit named four:
- Fixture repeatability — board pose variation within the tolerance that keeps fine traces inside the depth of field; the conditional-go on trace opens is void if pose wanders.
- Exposure stability across shifts — plant lighting bleeding into the enclosure changes the specular signature; the enclosure has to be light-tight, not merely shaded.
- Cycle-time headroom — enough slack per board for the capture strategy the borderline classes require, including multi-frame capture if the lighting retrofit is chosen.
- Vibration at capture — conveyor-induced blur at the pixels-per-mm the trace classes need is a harder constraint than at the resolution the bridging class needs.
Each condition maps to a class in the table. That mapping is what makes the document actionable: a plant manager can see that relaxing fixture tolerance costs the trace-opens verdict specifically, not “accuracy” generally.
The false-positive side of the cost case
Detection rate is the number everyone asks for. On a printed-electronics line the false-positive rate at target throughput is usually the number that decides the economics. Every false call routes a board to rework triage, and triage is a human inspector reading an image and a board — the exact cost the deployment was supposed to displace.
So the audit states a false-positive ceiling per class, derived from the line’s own numbers: boards per shift, minutes per triage event, and the inspector hours actually available. On this workload the ceiling for the paste classes was tight enough that a threshold tuned for maximum recall pushed triage load past the labour it displaced. The correct engineering response was to lower recall on the shallow-void class and keep that class in the manual sampling loop, rather than to claim both rates at once. Where the whole-line cost arithmetic gets built out, including which inspector hours genuinely disappear, sits with our comparison of CV inspection versus manual inspection on total cost.
The comparison baseline throughout is cost per board under the current regime — inspector hours, escape rate, rework cost — not a model score. Practitioners building CV pipelines against this kind of constraint set will find the underlying engineering approach on our computer vision page, and the audit itself is scoped as a defined engagement under services.
What the go/no-go document says
For this line the answer was a conditional go. Three classes greenlit at stated accuracy bands and a stated false-positive ceiling; trace opens greenlit contingent on an optics upgrade with a named pixels-per-mm target; shallow paste voids greenlit contingent on a lighting retrofit and cycle-time renegotiation, with the fallback of leaving that class with manual sampling; sub-pad voids and warp excluded on physics with the alternative inspection technology named. The pilot was then sized only around the greenlit classes.
A conditional go is not a softer yes. It is a yes with the failure conditions written down before anyone spends money, which is the only form of yes worth having on a line where the defect mix looks uniform on a datasheet and is not.
Frequently Asked Questions
What does CV inspection feasibility applied to a printed-electronics workload mean in practice? CV Inspection Feasibility Printed answers cleanly when you separate two things. With CV Inspection Feasibility Printed, the detail that matters is this. It means profiling this line’s own defect classes against this line’s own imaging conditions, then stating an achievable accuracy band per class. In practice that is a catalogue built from plant QA records, measurements of how each class behaves under the available lighting geometry and conveyor speed, and a go/no-go verdict per class rather than one figure for the board.
Which printed-electronics defect classes come out feasible, and which come out borderline or no-go? On the workload above, bridging and shorts, print registration drift, and paste smearing came out feasible at line speed. Hairline trace opens and shallow surface paste voids came out conditional on an optics or lighting change. Deep sub-pad voids and substrate warp came out no-go for 2D imaging because the defect is not surface-visible in intensity data at all.
How do reflective substrates and solder-paste specularity constrain achievable accuracy? Specular highlight from a reflective pad can saturate exactly the region where a shallow void’s intensity gradient would appear, so the information never reaches the model. Recovering it requires multi-angle or structured illumination, and both consume capture time the conveyor budget may not have. That coupling — lighting fix versus cycle time — is the real constraint, not model capacity.
What conditions must the line hold for measured accuracy to survive at production throughput? Fixture repeatability tight enough to keep fine features in the depth of field, exposure stability across shifts in a light-tight enclosure, cycle-time headroom for the capture strategy the borderline classes need, and vibration low enough not to blur at the required pixels-per-mm. Each condition ties to specific classes, so relaxing one voids a named verdict rather than degrading accuracy in general.
What false-positive ceiling is acceptable before CV inspection costs more than the manual inspection it replaces? The ceiling is derived from the line’s own arithmetic: boards per shift, minutes per rework-triage event, and the inspector hours actually available. When a recall-maximising threshold generates more triage load than the labour it displaces, the ceiling has been crossed — and the right move is to lower recall on the worst class and keep it in manual sampling, not to claim both rates.
What does a conditional go look like on a printed-electronics line? It names the greenlit classes with accuracy bands and a false-positive ceiling, names each borderline class with the specific optics, lighting, or fixturing change it depends on and the target that change must hit, and excludes the physics-limited classes while naming the alternative inspection technology. The pilot is then sized only around the greenlit set.
Printed electronics changes every assumption
Substrate variability, conductive ink behavior, and layer registration errors create a defect profile that standard CV models weren’t trained to recognize. Revisit it when your workload shifts.
